1. Field of the Invention
The invention relates to the field of integrated circuit testing, and in particular to a system and method for determining the signal delay contributions from specific process layers.
2. Related Art
The performance of an integrated circuit (IC) is largely determined by its timing characteristics (i.e., the speed at which signals propagate through the IC). This signal propagation speed is typically analyzed via standalone testing systems that interface with dedicated test structures formed on the IC chip. Note that the term “IC chip” refers to the combination of the IC (i.e., the circuit structures and devices that provide the desired functionality, such as a field programmable gate array (FPGA) or an complex programmable logic device (CPLD)) and the die, or substrate, on which the IC is formed. Because a large number of IC chips are manufactured simultaneously on a single wafer, the die area is larger than the IC area, to allow for scribe line regions between ICs. The scribe line regions allow the wafer to be sawn apart into individual IC chips without risk of damage to the ICs.
The scribe line regions also provide locations for the dedicated test structures used in conventional IC test techniques. For example, FIG. 1 shows a conventional IC chip 100 that includes an FPGA 110 formed on a die 120. FPGA 110 includes multiple configurable logic blocks (CLBs) 111, multiple input/output blocks (IOBs) 112, and a programmable interconnect matrix 113 that routes signals between the CLBs and IOBs. CLBs 111, IOBs 112, and interconnect matrix 113 are programmable by a user to provide a desired functionality for IC chip 100.
IC chip 100 also includes a scribe line test circuit 131 and a test pad 132 formed in a scribe line region 121 of die 120. Scribe line test circuit 131 is typically a ring oscillator (series of inverters) coupled to a load that is intended to be representative of the electrical behavior of FPGA 100. The output frequency of the ring oscillator is measured at test pad 132, and this frequency is used to derive a signal propagation speed value. A substantial difference between this derived signal propagation speed and the expected signal propagation speed for FPGA 110 can indicate a design or manufacturing problem associated with IC chip 100.
Unfortunately, this “external” measurement technique can be less than ideal in many circumstances. First, because scribe line test circuit 131 is external to FPGA 110, the devices and structures within circuit 131 may not accurately match the devices and structures within FPGA 100. The environment within FPGA 110 (e.g., thermal and electrical conditions) can be very different from the isolated environment in which scribe line test circuit 131 is located. Therefore, dimensional similarity between the circuit 131 and FPGA 110 may not be enough to provide performance similarity.
Also, because the frequency measurement must be taken by an external measurement system (via test pad 132), the technique can be very time consuming. This makes it infeasible to test all the ICs on a wafer (conventional testing systems typically only inspect about five dies per wafer), and so localized manufacturing problems may not be detected.
In addition; the electrical connection that must be made between the test probe of the external measurement system and test pad 132 introduces various parasitic effects into the measurement. Furthermore, the external measurement system will typically have an operating frequency below 1 MHz, and therefore forces scribe line test circuit 131 to operate at a frequency far below the normal operating range of FPGA 110 (which can have an operating frequency in the 200-300 MHz range). These measurement inaccuracies can significantly skew the final measurement results.
However, perhaps the most significant limitation associated with this conventional measurement technique is that it only provides a “bulk” reading of IC performance, and there is no way to determine the actual source of any unexpected signal propagation delays. This is problematic, since any subsequent troubleshooting of IC performance degradation must therefore involve a comprehensive, and hence inefficient, methodology that examines all the different IC components.
Accordingly, it is desirable to provide a method and structure for efficiently analyzing the performance of an IC and determining the source of any unexpected performance degradation.